Design of FPGA Macro Block Placement Algorithm Based on Objective Function
(1.College of Physics Science and Information Engineering,Jishou University,Jishou 416000,Hunan China;2.Chenzhou Vocational College of Technology,Chenzhou 423000,Hunan China)
[1] SHI Jian-zhong,AKASH RANDHAR,DINESH BHATIA.Macro Block Based FPGA Floorpanning [C]//10th International Conference on VLSI Design.Berlin:Springer,1997:57-60. [2] CHENG Lei,MARTIN D F WONG.Floorplan Design for Multi-Million Gate FPGAs [C]//ICAD Conference,Toronto:University of Tororto,2004.[3] MORTEZA SAHEB ZAMANI , MASOUD SOLEIMANI. Rectilinear Floorplanning of FPGAs Using Kohonen Map Neural Networks[C]//Proceedings of the International Joint Conference.Beijing:[s.n.],2003.[4] VAUGHN BETZ, JONATHAN ROSE.VPR:A New Packing,Placement and Routing Tool for FPGA Research [C]//Proceedings of Seventh International Workshop.UK.:Oxford,1997.[5] MURATA H,FUJIYOSHI H,NAKATAKE S,et al. VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair [J].IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems,1996,15(12):1 518-1 524.[6] PATEL C,COZZIE A,SCHMIT H.An Architectural Exploration of Via Patterned Gate Arrays [C]//Proceedings of the 2003 International Symposium on Physical Design.Beijing:[s.n.],2003:184-189.